This invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device wherein the distribution of an impurity in a gate electrode is improved.
When a gate electrode is provided during the manufacture of a MOS type semiconductor apparatus, gate oxide layer 2 is first deposited on the surface of silicon substrate 1, and then polycrystalline silicon layer 3 is mounted on the whole surface of said gate oxide layer 2 (FIG. 1). Next, an impurity, boron for example, is diffused through polycrystalline silicon layer 3 to convert said layer 3 into the p.sup.+ conductivity type to reduce resistance. The conventional process of diffusing boron through a polycrystalline silicon layer is represented by the types illustrated in FIGS. 2 to 4.
The process shown in FIG. 2 comprises the step of alternately arranging wafer 4 and plate-shaped boron nitride (BN) 5 on wafer support 6, and introducing boron into polycrystalline silicon layer 3 from boron nitride (BN) 5 by means of solid phase diffusion.
The process illustrated in FIG. 3 consists of placing a plurality of wafers 4 on wafer support 6 and introducing boron into a polycrystalline silicon layer by the vapor phase diffusion process involving the application of a gaseous atmosphere of boron trichloride (BCl.sub.3).
The process set forth in FIG. 4 comprises the step of diffusing boron ion B.sup.+ into polycrystalline silicon layer 3 for activation after ion-implanting.
However, the above-mentioned conventional semiconductor apparatus manufacturing methods are all accompanied with the following drawbacks.
To begin with, when the solid phase boron diffusion is carried out from boron nitride (BN), it is necessary to apply heat treatment at a temperature ranging from 900.degree. to 1000.degree. C. for about 90 to 120 minutes in order to ensure the uniform distribution of boron throughout polycrystalline silicon layer 3. However, gate oxide layer 2 used with a minute MOS transistor is as thin as 100 to 150 .ANG., and further is possessed of a large boron diffusion coefficient. If, therefore, the abovementioned high temperature heat treatment is performed for very long, boron undesirably tends to diffuse into substrate 1 beyond gate oxide layer 2, thereby giving rise to a drop in the withstand voltage of gate oxide layer 2 and variations in the threshold voltage of the resultant transistor. Consequently, the conventional solid phase boron diffusion from boron nitride BN presents difficulties in providing a minute transistor having thin gate oxide layer 2.
Further, the vapor phase boron diffusion in an gaseous atmosphere of boron trichloride (BCl.sub.3) also involves the same conditions as in the case of solid phase boron diffusion from boron nitride (BN) and encounters the above-mentioned difficulties.
On the other hand, the implantation of boron ion B.sup.+ is accompanied with the drawbacks that since the boron source is far from the polycrystalline silicon layer, and channeling readily takes place, it is impossible to ensure a peak boron concentration in the depth of polycrystalline silicon layer. When, therefore, polycrystalline silicon layer 3 has a thickness of 4000 .ANG., the acceleration energy of B.sup.+ is set at about 40 keV, and the region of peak boron concentration is set at a point about 1300 .ANG. from the surface of polycrystalline layer 3. If, in this case, it is desired to ensure a uniform boron concentration in polycrystalline silicon layer 3, it will be necessary to perform annealing at a temperature of 950.degree. C. for more than 2 hours. However, annealing continued for such a long time is accompanied with the drawbacks that boron is diffused into silicon substrate 1 beyond gate oxide layer 2 as in the aforementioned case, leading to a drop in the withstand voltage of gate oxide layer 2 and variations in the threshold voltage of a transistor.
Further, the literature "A JMOS Transistor Fabricated with 100-.ANG. Low-Pressure Nitrided-Oxide Gate Dielectric (IEEE TRANSACTIONS ON ELECTRON DEVICES VOL, ED-31 NO. 1, JANUARY 1984 P.18 by author Charles G. Sodini et al) discloses a process of depositing a silicon oxide layer on a silicon substrate, mounting a thin silicon nitride layer on said silicon oxide layer, ion-implanting boron in the resultant polycrystalline silicon layer, performing annealing at a predetermined temperature and for a preserved length of the time, thereby effecting the diffusion of boron in an activated state. In this proposed process, the thin silicon nitride layer prevents boron from diffusing into the silicon substrate beyond the gate oxide layer. However, the silicon nitride layer is generally required to have as small a thickness as about 100 .ANG.. But the formation of such a thin silicon nitride layer is difficult for the present-day technique of fabricating a thin layer. Moreover, the process disclosed in the above-mentioned literature involves an additional step of providing a thin silicon nitride layer, thus complicating the manufacturing process by that extent.